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this is information on a product in full production. march 2014 docid026035 rev 1 1/32 A22H165M high-performance class-g stereo headphone amplifier with i2c volume control datasheet - production data features ? power supply range: 2.3 v to 4.8 v ? 0.6 ma/channel quiescent current ? 2.1 ma current consumption with 100 w/channel (10 db crest factor) ? 0.006% typical thd+n at 1 khz ? 100 db typical psrr at 217 hz ? 100 db of snr a-weighted at g = 0 db ? zero pop and click ? i2c interface for volume control ? digital volume control range from -60 db to +4 db ? independent right and left channel shutdown control ? integrated high-efficiency buck converter ? low software standby current: 5 a max ? output coupling capacitors removed ? thermal shutdown and short-circuit protection ? flip-chip package: 1.65 mm x 1.65 mm, 400 m pitch, 16 bumps applications ? cellular /smart phones, portable media players ? wearable ? fitness and healthcare description the A22H165M is a class-g stereo headphone driver dedicated to high audio performance, high power efficiency and space-constrained applications such as wearable and fitness. it is based on the core technology of a low power dissipation amplifier combined with a high efficiency buck converter for supplying this amplifier. when powered by a battery, the buck converter generates the appropriate voltage to the amplifier depending on the amplitude of the audio signal to supply the headsets. it achieves a total 2.1 ma current consumption at 100 w output power (10 db crest factor). thd+n is 0.02% maximum at 1 khz and psrr is 100 db at 217 hz, which ensures a high audio quality of the device in a wide range of environments. the traditionally bulky ou tput coupling capacitors can be removed. a dedicated common-mode sense pin removes parasitic ground noise. the A22H165M is designed to be used with an output serial resistor. it ensures unconditional stability over a wide range of capacitive loads. the A22H165M is packaged in a tiny 16-bump flip-chip package with a pitch of 400 m. A22H165M - flip-chip avdd sw inl- c1 cms sda agnd c2 hpvdd voutl voutr inl+ inr+ pvss scl inr- 4321 a b c d avdd sw inl- c1 cms sda agnd c2 hpvdd voutl voutr inl+ inr+ pvss scl inr- 4321 a b c d pinout (top view) balls are underneath www.st.com
contents A22H165M 2/32 docid026035 rev 1 contents 1 absolute maximum ratings and operating c onditions . . . . . . . . . . . . . 3 2 typical application sche matic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.1 i2c bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.1.1 i2c bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.1.2 control register cr2 - address 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1.3 control register cr1 - address 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.2 wake-up and standby time definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.3 common mode sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
docid026035 rev 1 3/32 A22H165M absolute maximum ratings and operating conditions 32 1 absolute maximum ratings and operating conditions table 1. absolute maximum ratings symbol parameter value unit v cc supply voltage (1) during 1 ms. 1. all voltage values are measured with respect to the ground pin. 5.5 v v in+ ,v in- input voltage referred to ground +/- 1.2 v t stg storage temperature -65 to +150 c t j maximum junction temperature (2) 2. thermal shutdown is activated when maximum junction temperature is reached. 150 c r thja thermal resistance junction to ambient (3) 3. the device is protected from over-temperature by a thermal shutdown mechanism, active at 150 c. 200 c/w p d power dissipation internally limited (4) 4. exceeding the power derating curves for long periods may provoke abnormal operation. esd human body model (hbm) (5) all pins voutr, voutl vs. agnd 5. human body model: a 100 pf capacitor is charged to the specified voltage, then discharged through a 1.5 k resistor between two pins of the device. this is done for all couples of connected pin combinations while the other pins are floating. 2 4 kv machine model (mm), min. value (6) 6. machine model: a 200 pf capacitor is charged to the specified voltage, then discharged directly between two pins of the device with no external series resistor (internal resistor < 5 ). this is done for all couples of connected pin combinations whil e the other pins are floating. 100 v charge device model (cdm) all pins voutr, voutl 500 750 v iec61000-4-2 level 4, contact (7) iec61000-4-2 level 4, air discharge (7) 7. the measurement is performed on an evaluati on board, with esd protection emif02-av01f3. +/- 8 +/- 15 kv latch-up latch-up immunity 200 ma lead temperature (soldering, 10 sec) 260 c
absolute maximum ratings and operating conditions A22H165M 4/32 docid026035 rev 1 table 2. operating conditions symbol parameter value unit v cc supply voltage 2.3 to 4.8 v hpvdd buck dc output voltages high rail voltage low rail voltage 1.9 1.2 v sda, scl input voltage range gnd to v cc v r l load resistor 16 c l load capacitor serial resistor of 12 minimum, r l 16 0.8 to 100 nf t oper operating free air temperature range -40 to +85 c r thja flip-chip thermal resistance junction to ambient 90 c/w
docid026035 rev 1 5/32 A22H165M typical application schematic 32 2 typical application schematic figure 1. typical application schematic for the A22H165M table 3. A22H165M pin description pin n pin name pin definition a1 sw switching node of the buck converter a2 avdd analog supply voltage, connect to battery a3 voutl output signal for left audio channel a4 inl- negative input signal for left audio channel b1 agnd device ground b2 c1 flying capacitor terminal for internal negative supply generator b3 hpvdd buck converter output, power supply for amplifier b4 inl+ positive input signal for left audio channel c1 c2 flying capacitor terminal for internal negative supply generator c2 pvss negative supply generator output c3 cms common mode sense, to be connec ted as close as possible to the ground of headphone/line out plug c4 inr+ positive input signal for right audio channel d1 sda i2c data signal, up to v cc tolerant input d2 scl i2c clock signal, up to v cc tolerant input d3 voutr output signal for right audio channel d4 inr- negative input signal for right audio channel rout 12 ohms min. rout 12 ohms min. cout 0.8 nf min. cout 0.8 nf min. cin 2.2 uf cin 2.2 uf cin 2.2 uf cin 2.2 uf 1 2 3 j1 c12 2.2 uf cs 2.2 uf css 2.2 uf ct 10 uf l1 3.3 uh vbat i2c bus + - + - i2c negative supply positive supply agnd c1 c2 sda scl avdd inl- inl+ inr+ inr- voutl voutr cms level detector level detector sw hpvdd pvss negative left input positive left input negative right input positive right input am06119
typical application schematic A22H165M 6/32 docid026035 rev 1 table 4. A22H165M component description component value description cs 2.2 f decoupling capacitors for v cc . a 2.2 f capacitor is sufficient for proper decoupling of the A22H165M. an x5r dielectric and 10 v rating voltage is recommended to minimize c/ v when v cc =4.8v. must be placed as close as possible to the A22H165M to minimize parasitic inductance and resistance. c12 2.2 f capacitor for internal negative power supply operation. an x5r dielectric and 6.3 v rating voltage is recommended to minimize c/ v when hpvdd = 1.9 v. must be placed as close as possible to the A22H165M to minimize parasitic inductance and resistance. c ss 2.2 f filtering capacitor for internal negative power supply. an x5r dielectric and 6.3 v rating voltage is recommended to minimize c/ v when hpvdd = 1.9 v. c in input coupling capacitor that forms with z in /2 a first-order hi gh-pass filter with a -3 db cutoff frequency fc. for example, at maximum gain g = 4 db, z in = 12.5 k , c in = 2.2 f, therefore fc = 6 hz. c out 0.8 to 100 nf output capacitor of 0.8 nf minimum to 100 nf maximum. this capacitor is mandatory for operation of the A22H165M. r out 12 min. output resistor in-series wit h the A22H165M output. this 12 minimum resistor is mandatory for operation of the A22H165M. l1 3.3 h inductor for the buck converter. references of inductors: fdk: mipsz2012d3r3 (dc resistance = 0.19 , rated current = 0.8 a) murata: lqm2mpn3r3g0 (dc resistance = 0.12 , rated current = 1.2 a) c t 10 f tank capacitor for internal buck converter. an x5r dielectric and 6.3 v rating voltage is recommended to minimize c/ v when hpvdd = 1.9 v. esr of the c t capacitor must be as low as possible to obtain the best buck efficiency. cin 1 2 zinfc ----------------------- - =
docid026035 rev 1 7/32 A22H165M electrical characteristics 32 3 electrical characteristics v cc = +3.6 v, agnd = 0 v, t amb = 25 c (unless otherwise specified) v cc = +3.6 v, agnd = 0 v, r l = 32 + 15 , t amb = 25 c (unless otherwise specified) table 5. electrical characteristics of the i2c interface symbol parameter min. typ. max. unit v il low level input voltage on sda, scl pins 0.6 v v ih high level input voltage on sda, scl pins 1.2 v v ol low level output voltage, sda pin, i sink = 3 ma 0.4 v i in input current on sda, scl 10 a v sda scl , 600k -------------------------------- - table 6. electrical characteristics of the amplifier symbol parameter min. typ. max. unit i cc quiescent supply current, no input signal, both channels enabled 1.2 1.5 ma i s supply current, with input modulation, both channels enabled, hpvdd = 1.2 v, output power per channel, f=1khz pout = 100 w at 3 db crest factor pout = 500 w at 3 db crest factor pout = 1 mw at 3 db crest factor pout = 100 w at 10 db crest factor pout = 500 w at 10 db crest factor pout = 1 mw at 10 db crest factor 2.3 3.7 4.7 2.1 3.1 3.9 3.5 5 6.5 ma i stby standby current, no input signal, i2c cr1 = 01h v sda = 0 v, v scl = 0 v 0.6 5 a v in input differential voltage range (1) 1v rms v oo output offset voltage no input signal -500 +500 v v out maximum output voltage, in-phase signals r l = 16 , thd+n = 1% max, f = 1 khz r l = 47 , thd+n = 1% max, f = 1 khz r l = 10 k , s = 15 , l = 1 ?, thd+n = 1% max, f = 1 khz 0.6 1.0 1.0 0.8 1.1 1.3 v rms thd+n total harmonic distortion + noise, g = 0 db v out = 700 mvrms, f = 1 khz v out = 700 mvrms, 20 hz < f < 20 khz 0.006 0.05 0.02 %
electrical characteristics A22H165M 8/32 docid026035 rev 1 psrr power supply rejection ratio (1) , v ripple = 200 mv pp , grounded inputs f = 217 hz, g = 0 db, r l 16 f = 10 khz, g = 0 db, r l 16 90 100 70 db cmrr common mode rejection ratio f = 1 khz , g = 0 db, v ic = 200 mv pp f = 20 hz to 20 khz , g = 0 db, v ic = 200 mv pp 65 45 db crosstalk channel separation r l = 32 + 15 , g = 0 db, f = 1 khz, p o = 10 mw r l = 10 k , g = 0 db, f = 1 khz, v out =1 vrms 60 80 100 110 db snr signal-to-noise ratio, a-weighted, v out = 1 v rms , thd+n < 1%, f = 1 khz (1) g = +4 db g = +0 db 99 100 db onoise output noise voltage, a-weighted (1) g = +4 db g = +0 db 911 9 vrms g gain range with gain (db) = 20 x log[(v out l/r)/(inl/r+ - inl/r-)] -60 +4 db mute inl/r+ - inl/r- = 1 v rms -80 db - gain step size error -0.5 +0.5 step- size - gain error (g = +4 db) -0.45 +0.42 db z in differential input impedance 25 34 k input impedance during wake-up phase (referred to ground) 2 k z out output impedance when cr1 = 00 h (negative supply is on and amplifier output stages are off) (1) f < 40 khz f = 6 mhz f = 36 mhz 10 500 75 k t wu wake-up time (2) 12 16 ms t stby standby time 100 s t atk attack time. setup time between low rail buck voltage and high rail buck voltage 100 s t dcy decay time 50 ms 1. guaranteed by design and parameter correlation. 2. refer to the application information in section 4.3 on page 27 . table 6. electrical characteristi cs of the amplifier (continued) symbol parameter min. typ. max. unit
docid026035 rev 1 9/32 A22H165M electrical characteristics 32 figure 2. scl and sda timing diagram figure 3. start and stop condition timing diagram table 7. timing characteristics of the i2c interface for i2c interface signals over recommended operating conditions (unless otherwise specified) symbol parameter min. typ. max. unit f scl frequency, scl 400 khz t d(h) pulse duration, scl high 0.6 s t d(l) pulse duration, scl low 1.3 s t st1 setup time, sda to scl 100 ns t h1 hold time, scl to sda 0 ns t f bus free time between stop and start condition 1.3 s t st2 setup time, scl to start condition 0.6 s t h2 hold time, start condition to scl 0.6 s t st3 setup time, scl to stop condition 0.6 s scl sda t d(h) t d(l) t st1 t h1 am06113 am06114 t st3 scl sda t st2 start condition stop condition t h2 t f
electrical characteristics A22H165M 10/32 docid026035 rev 1 figure 4. current consumption vs. power supply voltage figure 5. standby current consumption vs. power supply voltage 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 no load; no input signal both channels enabled ta = 25 c quiscent supply current i cc (ma) power supply voltage vcc (v) no load; no input signal sda=scl = 0v ta = 25 c figure 6. maximum output power vs. load figure 7. maximum output power vs. load 10 100 1k 0 10 20 30 40 50 60 70 80 vcc=2.3v vcc=3.6v inputs = 0 , f = 1khz thd+n = 1% tamb = 25 c vcc=4.8v output power (mw) rl load resistance ( ) 10 100 1k 0 10 20 30 40 50 60 70 80 vcc=2.3v vcc=3.6v inputs = 180 , f = 1khz thd+n = 1% tamb = 25 c vcc=4.8v output power (mw) rl load resistance ( ) figure 8. maximum output power vs. power supply voltage figure 9. maximum output power vs. power supply voltage 2.3 2.7 3.1 3.5 3.9 4.3 4.7 0 20 40 60 80 100 120 thd+n=10% (180 ) thd+n=10% (0 ) thd+n=1% (0 ) rl = 16 , f = 1khz bw < 30khz, tamb = 25 c thd+n=1% (180 ) output power (mw) power supply voltage vcc (v) 2.3 2.7 3.1 3.5 3.9 4.3 4.7 0 20 40 60 80 thd+n=10% (180 ) thd+n=10% (0 ) thd+n=1% (0 ) rl = 32 , f = 1khz bw < 30khz, tamb = 25 c thd+n=1% (180 ) output power (mw) power supply voltage vcc (v)
docid026035 rev 1 11/32 A22H165M electrical characteristics 32 figure 10. maximum output power vs. power supply voltage figure 11. maximum output voltage vs. power supply voltage 2.3 2.7 3.1 3.5 3.9 4.3 4.7 0 20 40 60 thd+n=10% (180 ) thd+n=10% (0 ) thd+n=1% (0 ) rl = 47 , f = 1khz bw < 30khz, tamb = 25 c thd+n=1% (180 ) output power (mw) power supply voltage vcc (v) 2.3 2.7 3.1 3.5 3.9 4.3 4.7 700 800 900 1000 1100 1200 1300 1400 1500 1600 10 k 600 60 47 16 f = 1khz bw < 30khz, tamb = 25 c inputs = 0 , thd+n = 1% 32 output voltage (mvrms) power supply voltage vcc (v) figure 12. maximum output voltage vs. power supply voltage figure 13. current consumption vs. total output power 2.3 2.7 3.1 3.5 3.9 4.3 4.7 700 800 900 1000 1100 1200 1300 1400 1500 1600 10 k 600 60 47 16 f = 1khz bw < 30khz, tamb = 25 c inputs = 180 , thd+n=1% 32 output voltage (mvrms) power supply voltage vcc (v) 0.1 1 10 1 10 100 vcc=4.8v vcc=3.6v vcc=2.3v both channels enabled rl = 16 , f = 1khz ta = 25 c crest factor = 3db supply current i s (ma) total output power (mw) figure 14. current consumption vs. total output power figure 15. current consumption vs. total output power 0.1 1 10 1 10 100 vcc=4.8v vcc=3.6v vcc=2.3v both channels enabled rl = 32 , f = 1khz ta = 25 c crest factor = 3db supply current i s (ma) total output power (mw) 0.1 1 10 1 10 100 vcc=4.8v vcc=3.6v vcc=2.3v both channels enabled rl = 47 , f = 1 khz ta = 25 c crest factor = 3db supply current i s (ma) total output power (mw)
electrical characteristics A22H165M 12/32 docid026035 rev 1 figure 16. current consumption vs. total output power figure 17. power dissipation vs. total output power 0.1 1 1 10 100 crest factor=3db crest factor=10db both channels enabled rl = 47 , f = 1khz ta = 25 c, vcc = 3.6v supply current i s (ma) total output power (mw) 0.1 1 10 1 10 100 r = 47 r = 32 r = 16 both channels enabled f = 1khz, ta = 25 c crest factor = 3db power dissipation (mw) total output power (mw) figure 18. output impedance vs. frequency figure 19. differential input impedance vs. gain input floating input grounded vcc=2.3v to 4.8v hiz; right & left osc level=0.5v rms ta = 25 c -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 30 40 50 60 70 80 vcc=2.3v to 4.8v ta = 25 c differential input impedance (k ) gain (db) figure 20. thd+n vs. output power figure 21. thd+n vs. output power f=80hz f=1khz f=8khz vcc = 2.5v, rl = 16 g = 4db, inputs = 0 bw < 30khz, tamb = 25 c f=80hz f=1khz f=8khz vcc = 2.5v, rl = 16 g = 4db, inputs = 180 bw < 30khz, tamb = 25 c
docid026035 rev 1 13/32 A22H165M electrical characteristics 32 figure 22. thd+n vs. output power figure 23. thd+n vs. output power f=80hz f=1khz f=8khz vcc = 3.6v, rl = 16 g = 4db, inputs = 0 bw < 30khz, tamb = 25 c f=80hz f=1khz f=8khz vcc = 3.6v, rl = 16 g = 4db, inputs = 180 bw < 30khz, tamb = 25 c figure 24. thd+n vs. output power figure 25. thd+n vs. output power f=80hz, 1khz f=8khz vcc = 4.8v, rl = 16 g = 4db, inputs = 0 bw < 30khz, tamb = 25 c f=80hz, 1khz f=8khz vcc = 4.8v, rl = 16 g = 4db, inputs = 180 bw < 30khz, tamb = 25 c figure 26. thd+n vs. output power figure 27. thd+n vs. output power f=80hz f=1khz f=8khz vcc = 2.5v, rl = 32 g = 4db, inputs = 0 bw < 30khz, tamb = 25 c f=80hz f=1khz f=8khz vcc = 2.5v, rl = 32 g = 4db, inputs = 180 bw < 30khz, tamb = 25 c
electrical characteristics A22H165M 14/32 docid026035 rev 1 figure 28. thd+n vs. output power figure 29. thd+n vs. output power f=80hz f=1khz f=8khz vcc = 3.6v, rl = 32 g = 4db, inputs = 0 bw < 30khz, tamb = 25 c f=80hz f=1khz f=8khz vcc = 3.6v, rl = 32 g = 4db, inputs = 180 bw < 30khz, tamb = 25 c figure 30. thd+n vs. output power figure 31. thd+n vs. output power f=80hz f=1khz f=8khz vcc = 4.8v, rl = 32 g = 4db, inputs = 0 bw < 30khz, tamb = 25 c f=80hz f=1khz f=8khz vcc = 4.8v, rl = 32 g = 4db, inputs = 180 bw < 30khz, tamb = 25 c figure 32. thd+n vs. output power figure 33. thd+n vs. output power f=80hz f=1khz f=8khz vcc = 2.5v, rl = 47 g = 4db, inputs = 0 bw < 30khz, tamb = 25 c f=80hz f=1khz f=8khz vcc = 2.5v, rl = 47 g = 4db, inputs = 180 bw < 30khz, tamb = 25 c
docid026035 rev 1 15/32 A22H165M electrical characteristics 32 figure 34. thd+n vs. output power figure 35. thd+n vs. output power f=80hz f=1khz f=8khz vcc = 3.6v, rl = 47 g = 4db, inputs = 0 bw < 30khz, tamb = 25 c f=80hz f=1khz f=8khz vcc = 3.6v, rl = 47 g = 4db, inputs = 180 bw < 30khz, tamb = 25 c figure 36. thd+n vs. output power figure 37. thd+n vs. output power f=80hz f=1khz f=8khz vcc = 4.8v, rl = 47 g = 4db, inputs = 0 bw < 30khz, tamb = 25 c f=80hz f=1khz f=8khz vcc = 4.8v, rl = 47 g = 4db, inputs = 180 bw < 30khz, tamb = 25 c figure 38. thd+n vs. frequency figure 39. thd+n vs. frequency po=1mw po=15mw rl = 16 vcc = 2.5v g = 0db inputs = 0 bw < 20khz tamb = 25 c 20k 20 po=1mw po=15mw rl = 16 vcc = 2.5v g = 0db inputs = 180 bw < 20khz tamb = 25 c 20k 20
electrical characteristics A22H165M 16/32 docid026035 rev 1 figure 40. thd+n vs. frequency figure 41. thd+n vs. frequency po=1mw po=15mw rl = 16 vcc = 3.6v g = 0db inputs = 0 bw < 20khz tamb = 25 c 20k 20 po=1mw po=15mw rl = 16 vcc = 3.6v g = 0db inputs = 180 bw < 20khz tamb = 25 c 20k 20 figure 42. thd+n vs. frequency figure 43. thd+n vs. frequency po=1mw po=15mw rl = 16 vcc = 4.8v g = 0db inputs = 0 bw < 20khz tamb = 25 c 20k 20 po=1mw po=15mw rl = 16 vcc = 4.8v g = 0db inputs = 180 bw < 20khz tamb = 25 c 20k 20 figure 44. thd+n vs. frequency figure 45. thd+n vs. frequency po=1mw po=10mw rl = 32 vcc = 2.5v g = 0db inputs = 0 bw < 20khz tamb = 25 c 20k 20 po=1mw po=10mw rl = 32 vcc = 2.5v g = 0db inputs = 180 bw < 20khz tamb = 25 c 20k 20
docid026035 rev 1 17/32 A22H165M electrical characteristics 32 figure 46. thd+n vs. frequency figure 47. thd+n vs. frequency po=1mw po=10mw rl = 32 vcc = 3.6v g = 0db inputs = 0 bw < 20khz tamb = 25 c 20k 20 po=1mw po=10mw rl = 32 vcc = 3.6v g = 0db inputs = 180 bw < 20khz tamb = 25 c 20k 20 figure 48. thd+n vs. frequency figure 49. thd+n vs. frequency po=1mw po=10mw rl = 32 vcc = 4.8v g = 0db inputs = 0 bw < 20khz tamb = 25 c 20k 20 po=1mw po=10mw rl = 32 vcc = 4.8v g = 0db inputs = 180 bw < 20khz tamb = 25 c 20k 20 figure 50. thd+n vs. frequency figure 51. thd+n vs. frequency po=1mw po=10mw rl = 47 vcc = 2.5v g = 0db inputs = 0 bw < 20khz tamb = 25 c 20k 20 po=1mw po=10mw rl = 47 vcc = 2.5v g = 0db inputs = 180 bw < 20khz tamb = 25 c 20k 20
electrical characteristics A22H165M 18/32 docid026035 rev 1 figure 52. thd+n vs. frequency figure 53. thd+n vs. frequency po=1mw po=10mw rl = 47 vcc = 3.6v g = 0db inputs = 0 bw < 20khz tamb = 25 c 20k 20 po=1mw po=10mw rl = 47 vcc = 3.6v g = 0db inputs = 180 bw < 20khz tamb = 25 c 20k 20 figure 54. thd+n vs. frequency figure 55. thd+n vs. frequency po=1mw po=10mw rl = 47 vcc = 4.8v g = 0db inputs = 0 bw < 20khz tamb = 25 c 20k 20 po=1mw po=10mw rl = 47 vcc = 4.8v g = 0db inputs = 180 bw < 20khz tamb = 25 c 20k 20 figure 56. thd+n vs. frequency figure 57. thd+n vs. frequency vo=1vrms vo=100mvrms rl = rc network + 10k vcc = 2.3v to 4.8v g = 0db, inputs = 0 & 180 bw < 20khz, tamb = 25 c 20k 20 vo=1vrms vo=100mvrms rl = rc network + 600 vcc = 2.3v to 4.8v g = 0db, inputs = 0 & 180 bw < 20khz, tamb = 25 c 20k 20
docid026035 rev 1 19/32 A22H165M electrical characteristics 32 figure 58. thd+n vs. output voltage figure 59. thd+n vs. output voltage f=80hz f=1khz f=8khz rl = rc network + 10k vcc = 2.3v to 4.8v, g = 4db inputs = 0 & 180 bw < 30khz, tamb = 25 c f=80hz f=1khz f=8khz rl = rc network + 600 vcc = 2.3v to 4.8v, g = 4db inputs = 0 & 180 bw < 30khz, tamb = 25 c figure 60. thd+n vs. input voltage, hiz left and right figure 61. cmrr vs. frequency line in f=8khz line in f=1khz reference f=80hz, 1khz, 8khz line in f=80hz hiz left & right vcc = 2.3v to 4.8v zout generator = 1k bw < 30khz, tamb = 25 c 100 1000 10000 -80 -70 -60 -50 -40 -30 -20 -10 0 20k 20 100 1000 10000 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 g=-6db g=0db g=4db 20k 20 100 1000 10000 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 g=-6db g=0db g=4db 20k 20
electrical characteristics A22H165M 20/32 docid026035 rev 1 figure 64. psrr vs. frequency figure 65. output signal spectrum 100 1000 10000 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 g=-6db g=0db g=4db 20k 20 100 1000 10000 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 20k 20 100 1000 10000 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 20k 20 100 1000 10000 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 20k 20 100 1000 10000 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 20k 20
docid026035 rev 1 21/32 A22H165M electrical characteristics 32 figure 70. wake-up time figure 71. shutdown time vout 2ms/div 20mv/div sda 2 ms/div 1v/div vout 10s/div 100mv/div i2c ack after shutdown command
application information A22H165M 22/32 docid026035 rev 1 4 application information 4.1 i2c bus interface in compliance with the i2c protocol, the A22H165M uses a serial bus to control the chip?s functions with the clock (scl) and data (sda ) wires. these two lines are bi-directional (open collector) and require an external pull-up resistor (typically 10 k ). the maximum clock frequency in fast mode specified by the i2c standard is 400 khz, which the A22H165M supports. in this application, the A22H165M is always the slave device and the controlling microcontroller mcu is the master device. the slave address of the A22H165M is 1100 000x (c0h). table 8 summarizes the pin descriptions for the i2c bus interface. 4.1.1 i2c bus operation the host mcu can write to the A22H165M cont rol register to control the A22H165M, and read from the control register to obtain a configuration from the A22H165M. the A22H165M is addressed by the byte consisting of the 7-bit slave address and the r/w bit. there are four control registers ( table 10 ) named cr1 to cr4. in read mode, all the control registers can be accessed. in write mode, only cr1, cr2 and cr3 can be addressed. table 8. i2c bus interface pin descriptions pin functional description sda serial data pin scl clock input pin table 9. first byte after the start message for addressing the device a6 a5 a4 a3 a2 a1 a0 r/w 1100000x table 10. summary of control registers description register address d7 d6 d5 d4 d3 d2 d1 d0 cr1 1 hp_en_l hp_en_r 0 0 sc_l sc_r t_sh sws cr2 volume control 2 mute_l mute_r volume control 0 cr3 3 0 0 0 0 0 0 hiz_l hiz_r cr4 identification 4 0 1 000000
docid026035 rev 1 23/32 A22H165M application information 32 writing to the control registers to write data to the A22H165M, afte r the "start" message the mcu must: ? send the i2c 7-bit slave address and a low level for the r/w bit. ? send the register address to write to. ? send the data bytes (control register settings). all bytes are sent msb first. t he transfer of written data ends with a "stop" message. when transmitting several data bytes, the data can be written without having to repeat the "start" message or send the byte with the slave address. if several bytes are transmitted, they will be written repeatedly to cr1, cr2 and cr3. figure 72. i2c write operations reading from the control registers to read data from the A22H165M, after the "start" message the mcu must: ? send the i2c 7-bit slave address and a low level for the r/w bit. ? send the register address to write to. ? send the i2c 7-bit slave address and a high level for the r/w bit. ? receive the data (control register value). all bytes are read msb first. t he transfer of read data ends with a "stop" message. when transmitting several data bytes, the data can be read without having to repeat the "start" message or send the byte with the slave address. if several bytes are transmitted, they will be read repeatedly from cr1, cr2, cr3 and cr4. sda s 1100 0 0 ack 00 a7 d7 a0 a1 ack p start condition slave device address data bytes r/w acknowledge from slave acknowledge from slave stop condition a6 d6 d1 d0 d7 d6 d1 d0 register address cr x crx+1 ack ack am06115
application information A22H165M 24/32 docid026035 rev 1 figure 73. i2c read operations 4.1.2 control regist er cr2 - address 2 mute function: bits mute_l and mute_r in the volume register, mute_l and mute_r are dedicated to enabling the mute function, independently of the channel. when mute_l and mute_r are set to v ih , the mute function is enabled on the corresponding channel and the gain is set to -80 db. when mute_l and mute_r are set to v il , the i2c gain level is applied to the channel. am06116 sda s 110 000 ack 00 a7 a0 d7 p start condition device address data bytes r/w acknowledge fom slave not acknowledge stop condition d0 d7 d0 register address crx crx+1 ack a a s repeat start condition 110 001 00 ack ack device address r/w table 11. volume control register cr2 - address 2 volume control range: -60 db to +4 db d5 d4 d3 d2 d1 gain (in db) d5 d4 d3 d2 d1 gain (in db) 00000 -60 db 10000 -11 db 00001 -54 db 10001 -10 db 00010 -50.5 db 10010 -9 db 00011 -47 db 10011 -8 db 00100 -43 db 10100 -7 db 00101 -39 db 10101 -6 db 00110 -35 db 10110 -5 db 00111 -31 db 10111 -4 db 01000 -27 db 11000 -3 db 01001 -25 db 11001 -2 db 01010 -23 db 11010 -1 db 01011 -21 db 11011 0 db 01100 -19 db 11100 +1 db 01101 -17 db 11101 +2 db 01110 -15 db 11110 +3 db 01111 -13 db 11111 +4 db
docid026035 rev 1 25/32 A22H165M application information 32 4.1.3 control regist er cr1 - address 1 amplifier output short-circuit detection: bits sc_l and sc_r the amplifier?s outputs are protected from short-circuit that might accidentally occur during manipulation of the device. in a typical application, if a short-circuit arises on the jack plug, there will be no detection because of the serial resistor presen t on the amplifier output, thus the output curr ent threshold will not be reached. to be active, the detection has to occur dire ctly on the amplifier?s output with a signal modulation on the inputs of the A22H165M. this detection is depicted in figure 74 . figure 74. flowchart for short-circuit detection if a short-circuit is detected three consecutive times on one channel, a flag is raised in the i2c read register cr1. ? sc_l: equals 0 during normal operation, equal s 1 when a short-circuit is detected on the left channel. ? sc_r: equals 0 during normal operation, equa ls 1 when a short-circuit is detected on the right channel. the corresponding channel?s output stage is then set to high impedance mode. an i2c read command allows the reading of the sc_l and sc_r flags but does not reset them. an i2c write command has to be sent to cr1 to reset the flags to 0 and restore normal operation. am06117v1 counter = 0 power off counter = counter + 1 power on timeout = 40 ms power on wait 40 ms set flag sc_l or sc_r to 1 set flag hiz_l or hiz_r to 1 shortcut detection shortcut detection shortcut detection & timeout = 0 shortcut detection reset counter < 3 counter = 3
application information A22H165M 26/32 docid026035 rev 1 thermal shutdown protection: bit t_sh a thermal shutdown protection is implemented to protect the device from overheating. if the temperature rises above the thermal junction of 150c, the device is put into standby mode and a flag is raised in the read register cr1. ? t_sh: equals 0 during normal operation, equals 1 when a thermal shutdown is detected. when the temperature decreases to safe le vels, the circuit switches back to normal operation and the corresponding flag is cleared. software shutdown: bit sws when sws equals 1, the device is set to i2c software shutdown. when sws equals 0, the negative supply and buck converters are activated. channel activation: bits hp_en_l and hp_en_r when hp_en_l or hp_en_r equals 1, the corresponding amplifier channel is enabled. 4.2 wake-up and standby time definition the wake-up time of the A22H165M is guaranteed at 12 ms typical (refer to chapter 3: electrical characteristics on page 7 ). however, since the A22H165M is activated with an i2c bus, the wake-up start procedure is as follows. 1. the master sends a start bit. 2. the master sends the device address. 3. the slave (A22H165M) answers by an acknowledge bit. 4. the master sends the register address. 5. the slave (A22H165M) answers by an acknowledge bit. 6. the master sends the output mode configuration (cr1). 7. if the A22H165M was previously in standby mode, the wake-up starts on the falling edge of the eighth clock signal (s cl) corresponding to the cr1 byte. 8. after 12 ms (de-pop sequence time), the A22H165M outputs are operational. the standby time is guaranteed as 100 s typical (refer to chapter 3: electrical characteristics on page 7 ). however, since the A22H165M is de-activated with an i2c bus, the standby time operates as follows. 1. the master sends a start bit. 2. the master sends the device address. 3. the slave (A22H165M) answers by an acknowledge bit. 4. the master sends the register address. 5. the slave (A22H165M) answers by an acknowledge bit. 6. the master sends the output mode config uration (cr1), which corresponds, in this case, to standby mode. 7. the standby time starts on the falling edge of the eighth clock signal (scl) corresponding to the cr1 byte. 8. after 100 s, the A22H165M is in standby mode.
docid026035 rev 1 27/32 A22H165M application information 32 4.3 common mode sense the A22H165M implements a common-mode sense pin to correct any voltage differences that might occur between the return of the headphone jack and the gnd of the device and create parasitic noise in the headphone and/or line out. the solution to strongly reduce and practically eliminate this noise consists in connecting the headphone jack ground to the cms pin. this pin senses the difference of potential (voltage noise) between the A22H165M ground and the headphone ground. by way of the frequency response of the common-mode sense pin, this noise is removed from the A22H165M outputs.
package information A22H165M 28/32 docid026035 rev 1 5 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. figure 75. A22H165M footprint recommendation figure 76. pinout 150 m min. 400 m 400 m 400 m 400 m pcb pad size: = 260 m maximum = 220 m recommended 75 m min. 100 m max. trac k not soldered mask opening solder mask opening: = 300 m min (for 260 m diameter pad) pad in cu 18 m with flash niau (2-6 m, 0.2 m max.) top view (balls are underneath) bottom view avdd sw inl - c1 cms sda agnd c2 hpvdd voutl voutr inl+ inr+ pvss scl inr - 4321 a b c d c1 c2 hpvdd avdd agnd pvss cms voutr voutl inl+ inr+ inl - inr - scl sda sw 1234 a b c d
docid026035 rev 1 29/32 A22H165M package information 32 figure 77. marking (top view) figure 78. flip-chip - 16 bumps figure 79. device orientation in tape pocket ? logo: st ? symbol for lead-free: e ? part number: 21 ? x digit: assembly code ? date code: yww ? the dot marks pin a1 21x yww e 21x yww e 400 m m 400 m m 1650 m m 600 m m 1650 m m ? die size: 1.65 mm x 1.65 mm 30 m ? die height (including bumps): 600 m 55 m ? bump diameter: 250 m 40 m ? bump height: 205 m 35 m ? die height: 395 m 20 m ? pitch: 400 m 40 m ? coplanarity: 50 m max 4 1.5 user direction of feed 8 die size x + 70 m die size y + 70 m 4 all dimensions are in mm a 1 a 1
ordering information A22H165M 30/32 docid026035 rev 1 6 ordering information table 12. order codes order code temperature range package packing marking A22H165M -40c to +85c flip-chip tape & reel 21
docid026035 rev 1 31/32 A22H165M revision history 32 7 revision history table 13. document revision history date revision changes 06-mar-2014 1 initial release.
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